Integrated circuit fabrication may include formation of conductive interconnects across various regions of a semiconductor substrate. Some of the interconnects may be formed in high aspect ratio openings associated with regions having high density of circuit devices, and others of the interconnects may be formed in low aspect ratio openings.
It may be desired to simultaneously form the conductive interconnects within both the low aspect ratio openings and the high aspect ratio openings. However, difficulties may be encountered in attempting such simultaneous formation of the conductive interconnects due to conductive material overfilling the high aspect ratio openings before the low aspect ratio openings are filled. FIGS. 1 and 2 illustrate the prior art problem.
Referring to FIG. 1, a portion of a semiconductor construction 10 is illustrated. The semiconductor construction includes a base 12 over which an insulative material 14 is formed.
The base 12 may comprise a semiconductor wafer. For instance, base 12 may comprise, consist essentially of, or consist of, monocrystalline silicon lightly-doped with background p-type dopant. The terms “semiconductive substrate” and “semiconductor substrate” mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Base 12 is shown to be homogeneous in the illustration of FIG. 1 in order to simplify the drawing. The base may, however, comprise numerous different layers associated with integrated circuit fabrication. Such layers may, for example, comprise any of various conductive materials, insulative materials and semiconductor materials utilized in fabrication of various integrated circuit devices and interconnections.
Insulative material 14 may comprise any suitable composition or combination of compositions, and may, for example, comprise one or more of silicon dioxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), silicon nitride, silicon oxynitride, etc. Also, various conductive materials (not shown), may extend into insulative material 14 to electrically connect with other conductive materials formed over or through the insulative material.
Construction 10 is shown subdivided into two segments 16 and 18. Segment 16 comprises integrated circuit devices formed to high integration density, and may, for example, comprise a memory array. Segment 18 comprises integrated circuit devices formed to lower integration density, and may, for example, comprise logic devices.
Openings 20, 22, 24 and 26 extend into insulative material 14. The openings 20, 22 and 24 associated with segment 16 are formed to a higher aspect ratio than the opening 26 associated with segment 18.
An electrically conductive material 28 is formed over insulative material 14 and within openings 20, 22, 24 and 26. Material 28 may be a barrier material to prevent cross-diffusion between materials outside of openings 20, 22, 24 and 26, and other materials that will ultimately be formed within openings 20, 22, 24 and 26. For instance, if copper is ultimately to be formed within openings 20, 22, 24 and 26, then material 28 may be a barrier to copper diffusion, and may comprise, for example, one or more of tungsten, tantalum and tantalum nitride.
Referring to FIG. 2, conductive material 30 is formed within openings 20, 22, 24 and 26. Conductive material 30 may be formed in one or more plating steps, and may comprise, for example, one or more of copper, aluminum, ruthenium, tungsten, and other metals utilized in forming conductive interconnects. A problem with the formation of conductive material 30 is that high aspect ratio openings 20, 22 and 24 fill much faster than the low aspect ratio opening 26, and accordingly a large amount of overfill of conductive material 30 is formed over the high aspect ratio openings by the time that the low aspect ratio opening is filled. The excess material 30 may be removed by planarization (for instance, chemical-mechanical polishing (CMP)). However, the large amount of excess material 30 may create complications for the planarization which lead to dishing or other defects. Additionally, the large amount of excess material 30 leads to significant waste of the material 30, as well as to costs associated with removal and waste management.
It would be desirable to develop new methods which could alleviate or eliminate some or all of the above-discussed problems associated with prior art methods of simultaneously forming conductive materials within low aspect ratio openings and high aspect ratio openings.